| | | Topology |
In massively parallelized systems designers try to yielding low distances between nodes in the networks, to maintain low information transmission times with increasing numbers of CPU's. Our approach does not enfatize network topology. Each compinations of CPU and transmission tecnology yields good comunications performance up to a certain number of interconected units. The hardware designer should choose a good guess to form clusters of nodes which interconnect tightly with high performance. The clusters in turn would interconnect between themselfes with high cluster-to-cluster performance links.
The image shown in the previous section suggest, for example, that each node is conected to two busses. so that West-East propagation of Information would have to be routed via n clusters while North-South propagation would be handled by the direct bus connection. The following picture shows how to expand this approach to huge dimensions, without saturating the busses, at the cost of increased number of hops between distand nodes.
height=2in]tide/cluster.fig
The figure shows Clusters of eight CPU's, each of which has two connections, one to a West-Side bus and one to an East-Side bus. Let us observe the top rightmost four CPU's which are connected to one bus on their East-side. The upper two CPU's share their West-side bus with a North-Side located cluster, while the lower located two CPU's share their West-side bus with a South-Side located cluster.
As we argument later, locality of code and data will not be exploited by caching, but by automatic grouping the code around CPU's of nearby clusters.
| | | Topology |